이미 소장하고 있다면 판매해 보세요.
- 국내배송만 가능
- 문화비소득공제 가능
책소개
목차
|
Preface.
1 Introduction. 1.1 Mobile 3D Graphics. 1.2 Mobile Devices and Design Challenges. 1.2.1 Mobile Computing Power. 1.2.2 Mobile Display Devices. 1.2.3 Design Challenges. 1.3 Introduction to SoC Design. 1.4 About this Book. 2 Application Platform. 2.1 SoC Design Paradigms. 2.1.1 Platform and Set-based Design. 2.1.2 Modeling: Memory and Operations. 2.2 System Architecture. 2.2.1 Reference Machine and API. 2.2.2 Communication Architecture Design. 2.2.3 System Analysis. 2.3 Low-power SoC Design. 2.3.1 CMOS Circuit-level Low-power Design. 2.3.2 Architecture-level Low-power Design. 2.3.3 System-level Low-power Design. 2.4 Network-on-Chip based SoC. 2.4.1 Network-on-Chip Basics. 2.4.2 NoC Design Considerations. 2.4.3 Case Studies of Chip Implementation. 3 Introduction to 3D Graphics. 3.1 The 3D Graphics Pipeline. 3.1.1 The Application Stage. 3.1.2 The Geometry Stage. 3.1.3 The Rendering Stage. 3.2 Programmable 3D Graphics. 3.2.1 Programmable Graphics Pipeline. 3.2.2 Shader Models. 4 Mobile 3D Graphics. 4.1 Principles of Mobile 3D Graphics. 4.1.1 Application Challenges. 4.1.2 Design Principles. 4.2 Mobile 3D Graphics APIs. 4.2.1 KAIST MobileGL. 4.2.2 Khronos OpenGL-ES. 4.2.3 Microsoft’s Direct3D-Mobile. 4.3 Summary and Future Directions. 5 Mobile 3D Graphics SoC. 5.1 Low-power Rendering Processor. 5.1.1 Early Depth Test. 5.1.2 Logarithmic Datapaths. 5.1.3 Low-power Texture Unit. 5.1.4 Tile-based Rendering. 5.1.5 Texture Compression. 5.1.6 Texture Filtering and Anti-aliasing. 5.2 Low-power Shader. 5.2.1 Vertex Cache. 5.2.2 Low-power Register File. 5.2.3 Mobile Unified Shader. 6 Real Chip Implementations. 6.1 KAIST RAMP Architecture. 6.1.1 RAMP-IV. 6.1.2 RAMP-V. 6.1.3 RAMP-VI. 6.1.4 RAMP-VII. 6.2 Industry Architecture. 6.2.1 nVidia Mobile GPU ? SC10 and Tegra. 6.2.2 Sony PSP. 6.2.3 Imagination Technology MBX/SGX. 7 Low-power Rasterizer Design. 7.1 Target System Architecture. 7.2 Summary of Performance and Features. 7.3 Block Diagram of the Rasterizer. 7.4 Instruction Set Architecture (ISA). 7.5 Detailed Design with Register Transfer Level Code. 7.5.1 Rasterization Top Block. 7.5.2 Pipeline Architecture. 7.5.3 Main Controller Design. 7.5.4 Rasterization Core Unit. 8 The Future of Mobile 3D Graphics. 8.1 Game and Mapping Applications Involving Networking. 8.2 Moves Towards More User-centered Applications. 8.3 Final Remarks. Appendix Verilog HDL Design. A.1 Introduction to Verilog Design. A.2 Design Level. A.2.1 Behavior Level. A.2.2 Register Transfer Level. A.2.3 Gate Level. A.3 Design Flow. A.3.1 Specification. A.3.2 High-level Design. A.3.3 Low-level Design. A.3.4 RTL Coding. A.3.5 Simulation. A.3.6 Synthesis. A.3.7 Placement and Routing. A.4 Verilog Syntax. A.4.1 Modules. A.4.2 Logic Values and Numbers. A.4.3 Data Types. A.4.4 Operators. A.4.5 Assignment. A.4.6 Ports and Connections. A.4.7 Expressions. A.4.8 Instantiation. A.4.9 Miscellaneous. A.5 Example of Four-bit Adder with Zero Detection. A.6 Synthesis Scripts. Glossaries. Index. |
저자 소개
Hoi Jun Yoo is a Professor of Electrical Engineering at the Korea Advanced Institute of Science and Technology (KAIST) and currently serves as Project Manager for the Korea Ministry of Information and Communication's IT SoC and Post-PC programs. Yoo's industry experience includes time with Bell Communications Research in Red Bank, NJ, where he invented the two-dimensional phase-locked VCSEL array, the front-surface-emitting laser, and the high-speed lateral HBT, as well as an appointment as Manager of a DRAM design group at Hyundai Electronics. He has written popular Korean books on DRAM design and high performance DRAM, and in 1994 received the Electronic Industrial Association of Korea Award for his contribution to DRAM technology, along with the Korea Semiconductor Industry Association Award in 2002. Yoo is the founder the System Integration and IP Authoring Research Center (SIPAC), a national-level center funded by the Korean government. Yoo holds a B.S. in Electronic Engineering from Seoul National University and an M.S. and Ph.D degrees in Electrical Engineering from KAIST.
Jeong-Ho Woo is a PhD candidate at KAIST. Ju-Ho Sohn works at LG Electronics, and Byung-Gyu Nam works for Samsung.
품목정보
- 발행일
- 2010년 04월 27일
- 쪽수, 무게, 크기
- 344쪽 | 크기확인중
- ISBN13
- 9780470823774
리뷰/한줄평0
상품정보안내
(판형과 판수 등이 다양한 도서는 찾으시는 도서의 ISBN을 알려 주시면 보다 빠르고 정확한 안내가 가능합니다.)
해외거래처에서 품절인 경우, 2차 거래선을 통해 유럽과 미국 출판사로 직접 수입이 진행될 수 있습니다.
수입 진행 시점으로 부터 2~3주가 추가로 소요되며, 해외에서도 유통이 원활하지 않은 도서는 품절 안내가 지연될 수 있습니다.
해당 경우, 문자와 메일로 별도 안내를 드리고 있사오니 마이페이지에서 휴대전화번호와 메일주소를 다시 한번 확인해주시기 바랍니다.
